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PD - 97129
IRFR1018EPbF IRFU1018EPBF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
HEXFET(R) Power MOSFET
D
G S
Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
60V 7.1m: 8.4m: 79A c 56A
D-Pak IRFR1018EPbF
I-Pak IRFU1018EPBF
G
D
S
Gate
Drain
Max.
79c 56c 56 315 110 0.76 20 21 -55 to + 175 300
Source
Units
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Wire Bond Limited) Pulsed Drain Current d Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery f Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case)
A W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy e Avalanche Current d Repetitive Avalanche Energy g 88 47 11 mJ A mJ
Thermal Resistance
Symbol
RJC RJA RJA
Parameter
Junction-to-Case k Junction-to-Ambient (PCB Mount) jk Junction-to-Ambient k
Typ.
--- --- ---
Max.
1.32 40 110
Units
C/W
Notes through are on page 2
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1
3/8/08
IRFR/U1018EPbF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
60 --- --- --- 0.073 --- --- 7.1 8.4 2.0 --- 4.0 --- --- 20 --- --- 250 --- --- 100 --- --- -100
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 47A g V VDS = VGS, ID = 100A A VDS = 60V, VGS = 0V VDS = 48V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync RG(int) td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Internal Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
110 --- --- --- ---
---
Conditions
VDS = 50V, ID = 47A ID = 47A VDS = 30V VGS = 10V g ID = 47A, VDS =0V, VGS = 10V VDD = 39V ID = 47A RG = 10 VGS = 10V g VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 60V i VGS = 0V, VDS = 0V to 60V h
--- 46 10 12 34 0.73 13 35 55 46 2290 270 130 390 630
--- 69 --- --- --- --- --- --- --- --- --- --- --- --- ---
S nC
--- --- --- --- --- --- --- Effective Output Capacitance (Energy Related)h --- --- Effective Output Capacitance (Time Related)g
ns
pF
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) d Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- 79c 315 A
Conditions
MOSFET symbol showing the integral reverse
G D
S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 47A, VGS = 0V g VR = 51V, --- 26 39 ns TJ = 25C IF = 47A TJ = 125C --- 31 47 di/dt = 100A/s g --- 24 36 nC TJ = 25C TJ = 125C --- 35 53 --- 1.8 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 56A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.08mH RG = 25, IAS = 47A, VGS =10V. Part not recommended for use above this value. ISD 47A, di/dt 1668A/s, VDD V(BR)DSS, TJ 175C.
Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C.
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
2
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IRFR/U1018EPbF
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
BOTTOM
100
BOTTOM
4.5V 10
10
4.5V
60s PULSE WIDTH
Tj = 25C 1 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) 1 0.1 1
60s PULSE WIDTH
Tj = 175C 10
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance (Normalized)
Fig 2. Typical Output Characteristics
2.5 ID = 47A 2.0 VGS = 10V
ID, Drain-to-Source Current (A)
100 TJ = 175C 10
1.5
1
TJ = 25C VDS = 25V
1.0
60s PULSE WIDTH 0.1 2 3 4 5 6 7 8 9
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
4000
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
16
VGS, Gate-to-Source Voltage (V)
ID= 47A VDS = 48V VDS = 30V VDS = 12V
3000
C, Capacitance (pF)
Ciss 2000
12
8
1000
Coss Crss 1 10 VDS , Drain-to-Source Voltage (V) 100
4
0
0 0 10 20 30 40 50 60 QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFR/U1018EPbF
1000
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R DS (on)
100
1000
TJ = 175C
100
1msec
10
100sec
TJ = 25C
10
LIMITED BY PACKAGE 10msec Tc = 25C Tj = 175C Single Pulse 0.1 1
1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD , Source-to-Drain Voltage (V)
1
DC 10 100
0.1 VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
80 LIMITED BY PACKAGE 60
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Fig 8. Maximum Safe Operating Area
80 Id = 5mA
ID, Drain Current (A)
75
40
70
20
65
0 25 50 75 100 125 150 175 TC, Case Temperature (C)
60 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Temperature ( C )
Fig 9. Maximum Drain Current vs. Case Temperature
0.8
Fig 10. Drain-to-Source Breakdown Voltage
400
EAS, Single Pulse Avalanche Energy (mJ)
350 300 250 200 150 100 50 0
0.6
ID 5.3A 11A BOTTOM 47A
TOP
Energy (J)
0.4
0.2
0.0 0 10 20 30 40 50 60
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
4
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFR/U1018EPbF
10
Thermal Response ( Z thJC )
1
D = 0.50 0.20
0.1
0.10 0.05 0.02 0.01
J J 1 1
R1 R1 2
R2 R2
R3 R3 3
R4 R4 C 4
2
3
4
0.01
Ci= i/Ri Ci i/Ri
Ri (C/W) 0.026741 0.28078 0.606685 0.406128
(sec)
0.000007 0.000091 0.000843 0.005884
SINGLE PULSE ( THERMAL RESPONSE )
0.001 1E-006 1E-005 0.0001 0.001
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.01 0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
Avalanche Current (A)
0.01
10
0.05 0.10
1
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C.
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
100
EAR , Avalanche Energy (mJ)
80
TOP Single Pulse BOTTOM 10% Duty Cycle ID = 47A
60
40
20
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150
Starting TJ , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFR/U1018EPbF
4.5
ID = 1.0A
14 12 10
IRR (A)
VGS(th) Gate threshold Voltage (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75
ID = 1.0mA ID = 250A ID = 100A
IF = 32A VR = 51V TJ = 25C TJ = 125C
8 6 4 2 0 0 200 400 600 800 1000 diF /dt (A/s)
100 125 150 175
TJ , Temperature ( C )
Fig 16. Threshold Voltage vs. Temperature
14 12 10
IRR (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
320 IF = 32A VR = 51V TJ = 25C TJ = 125C
IF = 47A VR = 51V TJ = 25C TJ = 125C
QRR (A)
280 240 200 160 120 80 40 0
8 6 4 2 0 0 200 400 600 800 1000 diF /dt (A/s)
0
200
400
600
800
1000
diF /dt (A/s)
Fig. 18 - Typical Recovery Current vs. dif/dt
320 280 240 200
QRR (A)
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 47A VR = 51V TJ = 25C TJ = 125C
160 120 80 40 0 0 200 400 600 800 1000 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFR/U1018EPbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
*
* * * *
dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
**
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* Use P-Channel Driver for P-Channel Measurements ** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
Fig 22b. Unclamped Inductive Waveforms
VDS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
90%
D.U.T.
+
VDS
-VDD
10%
VGS
td(on) tr td(off) tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT
20K 1K
S
VCC
Vgs(th)
Qgodr
Qgd
Qgs2 Qgs1
Fig 24a. Gate Charge Test Circuit
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Fig 24b. Gate Charge Waveform
7
IRFR/U1018EPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 16, 2001 IN T HE AS S EMBLY LINE "A" Note: "P" in as s embly line pos ition indicates "Lead-F ree" "P" in as s embly line pos ition indicates "Lead-F ree" qualification to the cons umer-level INT ERNAT IONAL RECT IF IER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFR120 116A 12 34
DAT E CODE YEAR 1 = 2001 WEEK 16 LINE A
OR
INT ERNAT IONAL RECT IF IER LOGO AS S EMBLY LOT CODE
PART NUMBER
IRFR120 12 34
DAT E CODE P = DES IGNAT ES LEAD-F REE PRODUCT (OPT IONAL) P = DES IGNAT ES LEAD-F REE PRODUCT QUALIF IED T O T HE CONS UMER LEVEL (OPT IONAL) YEAR 1 = 2001 WEEK 16 A = AS S EMBLY S IT E CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
8
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IRFR/U1018EPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: THIS IS AN IRFU120 WITH AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 2001 IN T HE AS S EMBLY LINE "A" Note: "P" in as s embly line pos ition indicates Lead-Free" INT ERNAT IONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 119A 56 78
DATE CODE YEAR 1 = 2001 WEEK 19 LINE A
OR
INT ERNAT IONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 56 78
DATE CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 1 = 2001 WEEK 19 A = AS S EMBLY S ITE CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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9
IRFR/U1018EPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice. This product has been designed for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.3/08
10
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